AD (Analog Devices) Articles
Analog Devices, Inc. (NYSE: ADI) defines innovation and excellence in signal processing. ADI's analog, mixed-signal, and digital signal processing (DSP) integrated circuits (IC) play a fundamental role in converting, conditioning, and processing real-world phenomena such as light, sound, temperature, motion, and pressure into electrical signals to be used in a wide array of electronic equipment. But that doesn’t begin to capture the essence of what Analog Devices does for our customers, and ultimately for the end user.
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- Parent Category: Product News
- Category: AD (Analog Devices) Articles
- Published on Thursday, 27 September 2012 09:12
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CrossCore Embedded Studio Eclipse-based IDE (Integrated Development Environment), allowing users to access a large ecosystem of third-party tools and technologies.
Beijing, September 21, 2012 / PRNewswire / - Analog Devices, Inc. (NASDAQ: ADI), a global leader in high-performance signal processing solutions supplier, has recently launched applies to Blackfin ® and SHARC ® Processors next-generation software development platform CrossCore ® Embedded Studio (CCES). CCES developed with the use of industry-standard open source Eclipse environment to support access to a rich ecosystem of proprietary and open source tools and technologies, so as to shorten the product development cycle, significantly faster time to market.
CCES Blackfin and SHARC developers to provide world-class C / C + + and assembly language editing environment, providing the drive and service support plug-ins, including Ethernet, USB, the algorithm software modules, operating system, file system. CCES also provide easy-to-use integrated multi-core development and debugging features.
CCES Blackfin and SHARC developers to provide world-class C / C + + and assembly language editing environment, providing the drive and service support plug-ins, including Ethernet, USB, the algorithm software modules, operating system, file system. CCES also provide easy-to-use integrated multi-core development and debugging features.
In addition to providing attractive IDE (Integrated Development Environment) experience, CCES provides Micrium's embedded software components support, such as uC / OS-IIITM Real-Time Kernel, uC / USB DeviceTM Stack and uC / FSTM the File System. This allows software developers able to access Micrium's strict development process developed by the industry's leading real-time operating system to achieve stable operation and meet strict coding standards, provide clear and concise documentation.
- Written by Super User
- Parent Category: Product News
- Category: AD (Analog Devices) Articles
- Published on Monday, 03 September 2012 05:12
- Hits: 153
Analog Devices, Inc. Recently launched a fully programmable jitter attenuation the dual clock converter IC (integrated circuit) AD9559 timing requirements to meet the high-speed fiber-optic transmission network (OTN) applications and high-density line cards. AD9559 four-input multi-service line adaptive clock converter can support a variety of standard frequency, suitable for all kinds of wired communications applications, including synchronous Ethernet, SONET / SDH, 1/10/100G Ethernet, Fibre Channel, as well as other require low jitter, high flexibility and fast time to market.
The The AD9559 converter IC can be any standard input frequency synchronization convert any standard output frequency up to 1.25 GHz, total jitter less than 400 fs RMS (root mean square) within the range of 12 kHz to 20 MHz integration bandwidth. AD9559 single-chip IC replaced two synchronized timing devices help designers to reduce board area and optimize costs.
The AD9559 is the industry's most flexible, high-performance dual adaptive clock conversion solutions, suitable for high-density line cards and OTN applications. Adaptive clock allows locking DPLL (digital PLL), while changing the the DPLL frequency division ratio. Therefore, the output frequency can be dynamically adjusted nominal output frequency range of + / - 100 ppm frequency resolution stepper less than 0.1 ppb loop without having to disconnect or reprogram the device. AD9559IC parallel PLL architecture allows the user to generate a completely independent output clock. Two DPLL can be synchronized with one of the four input reference clock, and each the DPLL can produce two output clock. The DPLL can reduce the external reference clock input time jitter or phase noise.
With digital control loop and hold circuits, even if all the reference clock are VALID, AD9559 can continuously generate clean (low jitter), the effective output clock. Take advantage of the the AD9559 clock converter built-in programming capability, network line card design engineers can use the same devices in many different circuit board design, to reduce the number of devices required and reduce the overall system cost.
The AD9559 clock converter size 10 mm x 10 mm, to facilitate line card design to obtain a compact, frequency agility, high cost of the clock. Suitable applications include data communications, a new generation of wired network applications, test and measurement, high-speed data acquisition, video applications, and wireless base station controllers.
Main features of the four-input dual adaptive clock converter AD9559
Dual PLL architecture, four reference input (single-ended or differential) with an input connected to the crossing point support the adaptive clock bandgap clock input reference, suitable for OTN demapping applications to support stability in the hold mode GR-1244 Stratum 3 smooth reference switching output phase almost no disturbance supports Telcordia GR-253 jitter generation, conversion and tolerance for SONET / SDH OC-192 system. ITU-T G.8262 synchronous Ethernet clock support ITU-T G.823, G.824, G.825 and G.8261
The The AD9559 converter IC can be any standard input frequency synchronization convert any standard output frequency up to 1.25 GHz, total jitter less than 400 fs RMS (root mean square) within the range of 12 kHz to 20 MHz integration bandwidth. AD9559 single-chip IC replaced two synchronized timing devices help designers to reduce board area and optimize costs.
The AD9559 is the industry's most flexible, high-performance dual adaptive clock conversion solutions, suitable for high-density line cards and OTN applications. Adaptive clock allows locking DPLL (digital PLL), while changing the the DPLL frequency division ratio. Therefore, the output frequency can be dynamically adjusted nominal output frequency range of + / - 100 ppm frequency resolution stepper less than 0.1 ppb loop without having to disconnect or reprogram the device. AD9559IC parallel PLL architecture allows the user to generate a completely independent output clock. Two DPLL can be synchronized with one of the four input reference clock, and each the DPLL can produce two output clock. The DPLL can reduce the external reference clock input time jitter or phase noise.
With digital control loop and hold circuits, even if all the reference clock are VALID, AD9559 can continuously generate clean (low jitter), the effective output clock. Take advantage of the the AD9559 clock converter built-in programming capability, network line card design engineers can use the same devices in many different circuit board design, to reduce the number of devices required and reduce the overall system cost.
The AD9559 clock converter size 10 mm x 10 mm, to facilitate line card design to obtain a compact, frequency agility, high cost of the clock. Suitable applications include data communications, a new generation of wired network applications, test and measurement, high-speed data acquisition, video applications, and wireless base station controllers.
Main features of the four-input dual adaptive clock converter AD9559
Dual PLL architecture, four reference input (single-ended or differential) with an input connected to the crossing point support the adaptive clock bandgap clock input reference, suitable for OTN demapping applications to support stability in the hold mode GR-1244 Stratum 3 smooth reference switching output phase almost no disturbance supports Telcordia GR-253 jitter generation, conversion and tolerance for SONET / SDH OC-192 system. ITU-T G.8262 synchronous Ethernet clock support ITU-T G.823, G.824, G.825 and G.8261
- Written by Super User
- Parent Category: Product News
- Category: AD (Analog Devices) Articles
- Published on Wednesday, 23 May 2012 04:51
- Hits: 212
Analog Devices, Inc. a global leader in high performance signal processing solutions provider, recently launched a series of multi-point low-voltage differential signaling (M-LVDS) transceiver ADN469xE, with the highest ESD in all multi-point LVDS transceiver (electrostatic Discharge) protection. ADN469xE the M-LVDS family consists of eight transceivers, each device can use a differential cable to connect 32 data / clock node and 100 Mbps or 200 Mbps data rate. In contrast, the traditional LVDS communication link must use 32 separate point-to-point node, which significantly increases power consumption, and connector size, the cable costs and board space. ADI's ADN469xE the M-LVDS Series 8 kV IEC ESD protection available, 11 times the M-LVDS transceivers competing products. This higher level of protection can improve the reliability of the pluggable boards and cards suitable for wireless base stations and network infrastructure, data acquisition, automated test equipment and other high-speed, high degree of network backplane and cable applications. ADI's ADN469xE transceiver provides half-duplex and full-duplex version is fully compatible with the TIA/EIA-899 M-LVDS standard. These new transceiver provides the following configuration:
· ADN4691E/ADN4693E: a receiver data rate up to 200 Mbps symmetry input threshold voltage, aimed at improving the clock timing performance
The the · ADN4696E/ADN4697E: data rates up to 200 Mbps receiver is designed for data applications, the receiver input threshold voltage offset of -100 mV. This bus is idle (bus idle fail-safe) or the input is disconnected (open circuit fail-safe), to ensure that the receiver output state is known.
Series of the main features of the ADN469xE M-LVDS Transceiver
• comply with the TIA-EIA 899 standard
ESD Protection: 15 kV HBM 8 kV IEC61000-4-2 Contact Discharge
Common mode range: -1 V to 3.4 V
Enhanced PSRR (jitter performance for the system)
Enhance the receiver input of the differential noise suppression performance
· Temperature range: -40 ˚ C to 85 ˚ C
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